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PH8253 Notes Physics for Electronics Engineering

PH8253 Notes Physics for Electronics Engineering

PH8253 Notes Physics for Electronics Engineering notes of regulation 2017 Anna University.

The Notes for PH8253 is available in pdf format to download. This subject Physics for Electronics Engineering is for second semester Anna University engineering students.

PH8253 Notes TEXT BOOKS:

1. Kasap, S.O. “Principles of Electronic Materials and Devices”, McGraw-Hill Education, 2007.
2. Umesh K Mishra & Jasprit Singh, “Semiconductor Device Physics and Design”, Springer, 2008.
3. Wahab, M.A. “Solid State Physics: Structure and Properties of Materials”. Narosa Publishing House, 2009.

PH8253 Notes REFERENCES:

1. Garcia, N. & Damask, A. “Physics for Computer Science Students”. Springer-Verlag, 2012.
2. Hanson, G.W. “Fundamentals of Nanoelectronics”. Pearson Education, 2009.
3. Rogers, B., Adams, J. & Pennathur, S. “Nanotechnology: Understanding Small Systems”. CRC Press, 2014.

Subject Name PHYSICS FOR ELECTRONICS ENGINEERING
Subject Code PH8253
Regulation 2017
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Download the notes of PH8253 Physics for Electronics Engineering Unit wise

First Unit notes  ELECTRICAL PROPERTIES OF MATERIALS click here to download

Second Unit notes click here to download


Third Unit notes MAGNETIC AND DIELECTRIC PROPERTIES OF MATERIALS click here to download


Fourth Unit notes OPTICAL PROPERTIES OF MATERIALS click here to download


Fifth Unit notes NANOELECTRONIC DEVICES click here to download


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PH8253 Question Paper


PH8253 PHYSICS FOR ELECTRONICS ENGINEERING Syllabus Click here


MA8251 Engineering Mathematics 2 Syllabus and notes click here


PH8201 Physics For Civil Engineering notes click here


BE8251 Basic Electrical and Electronics Engineering click here


HS8251 Syllabus Technical English Download  click here


GE8292 Engineering Mechanics Syllabus and notes click here


GE8261 Engineering Practices Laboratory syllabus click here


CE8211 Computer Aided Building Drawing syllabus click here


GE8291 Environmental Science and Engineering syllabus click here

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r2017 notes

BE8253 Notes Basic Electrical Electronics and Instrumentation Engineering

BE8253 Notes Basic Electrical Electronics and Instrumentation Engineering 

BE8253 Notes Basic Electrical Electronics and Instrumentation Engineering notes for regulation 2017 Anna University free download (be8253 lecture notes).

We have provided notes for Basic Electrical Electronics and Instrumentation Engineering in this page to download for students in pdf format.

BE8253 notes TEXT BOOKS

1. D P Kothari and I.J Nagarath, ‖Electrical Machines ―Basic Electrical and Electronics Engineering‖, McGraw Hill Education(India) Private Limited, Third Reprint ,2016.

2. Leonard S Bobrow, ― Foundations of Electrical Engineering‖, Oxford University Press, 2013.

3. Thereja .B.L., ―Fundamentals of Electrical Engineering and Electronics‖, S. Chand & Co. Ltd., 2008.

BE8253 notes REFERENCES

1. A.E.Fitzgerald, David E Higginbotham and Arvin Grabel, ―Basic Electrical Engineering‖, McGraw Hill Education(India) Private Limited, 2009.

2. Allan S Moris, ―Measurement and Instrumentation Principles‖, Elseveir, First Indian Edition, 2006. (be8253 lecture notes)

3. Del Toro, ―Electrical Engineering Fundamentals‖, Pearson Education, New Delhi, 2007.

4. John Bird, ―Electrical Circuit Theory and Technology‖, Elsevier, First Indian Edition, 2006. (be8253 lecture notes)

5. N K De, Dipu Sarkar, ―Basic Electrical Engineering‖, Universities Press (India)Private Limited 2016 6. Rajendra Prasad, ―Fundamentals of Electrical Engineering‖, Prentice Hall of India, 2006.

Subject Name BASIC ELECTRICAL, ELECTRONICS AND INSTRUMENTATION ENGINEERING
Subject Code BE8253
Regulation 2017
File PDF

Unit 1 ELECTRICAL CIRCUITS and Unit 2  Notes click here to download

3rd Unit Notes  click here to download


Unit 4 Notes click here to download


5th Unit Notes click here to download


BE8253 important questions Basic Electrical Electronics and Instrumentation Engineering


BE8253 Syllabus Basic Electrical Electronics and Instrumentation Engineering


BE8253 Question Bank Basic Electrical Electronics and Instrumentation Engineering


Other links

MA8251 Engineering Mathematics 2 Syllabus and notes click here


PH8201 Physics For Civil Engineering notes click here


BE8251 Basic Electrical and Electronics Engineering click here


GE8291 Environmental Science and Engineering syllabus click here


GE8292 Engineering Mechanics Syllabus and notes click here


GE8261 Engineering Practices Laboratory syllabus click here


CE8211 Computer Aided Building Drawing syllabus click here


HS8251 Syllabus Technical English Download  click here

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r2017 notes

PH8251 Notes Materials Science

PH8251 Notes Materials Science Regulation 2017 Anna University

PH8251 Notes Materials Science for regulation 2017 Anna University.

The subject ph8251 Materials Science is for semester 2 and the notes are available to students for downloading.

PH8251 Notes TEXT BOOKS:

1. Balasubramaniam, R. ―Callister’s Materials Science and Engineering‖. Wiley India Pvt. Ltd., 2014.

2. Raghavan, V. ―Physical Metallurgy: Principles and Practice‖. PHI Learning, 2015.

3. Raghavan, V. ―Materials Science and Engineering : A First course‖. PHI Learning, 2015.

PH8251 Notes REFERENCES:

1. Askeland, D. ―Materials Science and Engineering‖. Brooks/Cole, 2010.

2.Smith, W.F., Hashemi, J. & Prakash, R. ―Materials Science and Engineering‖. Tata McGraw Hill Education Pvt. Ltd., 2014.

3. Wahab, M.A. ―Solid State Physics: Structure and Properties of Materials‖. Narosa Publishing House, 2009.

Subject Name Materials Science
Subject Code PH8251
Regulation 2017
Semester 2

PH8251 Notes Unit Wise:

First unit PHASE DIAGRAMS click here to download

Second unit click here to download


Third unit MECHANICAL PROPERTIES click here to download


Fourth unit MAGNETIC and DIELECTRIC AND SUPERCONDUCTING MATERIALS click here to download


Fifth unit NEW MATERIALS click here to download


PH8251 Syllabus Materials Science Download  click here


Other links

MA8251 Engineering Mathematics 2 Syllabus and notes click here


PH8201 Physics For Civil Engineering notes click here


BE8251 Basic Electrical and Electronics Engineering click here


GE8291 Environmental Science and Engineering syllabus click here


GE8292 Engineering Mechanics Syllabus and notes click here


GE8261 Engineering Practices Laboratory syllabus click here


CE8211 Computer Aided Building Drawing syllabus click here


HS8251 Syllabus Technical English Download  click here

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r2017 notes

GE8291 Notes Environmental Science Engineering

GE8291 Notes Environmental Science Engineering

GE8291 Notes Environmental Science Engineering for regulation 2017 Anna University is provided in this page to download in pdf.

TEXTBOOKS for GE8291 Notes

1. Benny Joseph, ‘Environmental Science and Engineering’, Tata McGraw-Hill, New Delhi, 2006.
2. Gilbert M.Masters, ‘Introduction to Environmental Engineering and Science’, 2nd edition,Pearson Education, 2004.

REFERENCES with GE8291 Notes

1. Dharmendra S. Sengar, ‘Environmental law’, Prentice hall of India Pvt Ltd, New Delhi, 2007.
2. Erach Bharucha, “Textbook of Environmental Studies”, Universities Press(I) Pvt, Ltd, Hydrabad, 2015.
3. G. Tyler Miller and Scott E. Spoolman, “Environmental Science”, Cengage Learning India PVT, LTD, Delhi, 2014.
4. Rajagopalan, R, ‘Environmental Studies-From Crisis to Cure’, Oxford University Press, 2005.

Subject Name Environmental Science Engineering
Subject Code GE8291
Regulation 2017

GE8291 Notes Click here to download

 

GE8291 Syllabus Environmental Science and Engineering


GE8291 Important questions Environmental Science and Engineering


GE8291 Question Paper Environmental Science and Engineering


Other links

MA8251 Engineering Mathematics 2 Syllabus and notes click here


PH8201 Physics For Civil Engineering notes click here


BE8251 Basic Electrical and Electronics Engineering click here


HS8251 Syllabus Technical English Download  click here


GE8292 Engineering Mechanics Syllabus and notes click here


GE8261 Engineering Practices Laboratory syllabus click here


CE8211 Computer Aided Building Drawing syllabus click here


Civil Engineering subjects for regulation 2017


Mechanical Engineering (MECH) subjects for regulation 2017


Electrical and Electronics Engineering (EEE) subjects for regulation 2017


Electronics and Communication Engineering (ECE) subjects for regulation 2017


Computer Science and Engineering (CSE) subjects for regulation 2017


Information Technology (IT) subjects for regulation 2017

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r2017 notes

HS8251 Notes Technical English

HS8251 Notes Technical English

HS8251 Notes Technical English for Regulation 2017 is provided in pdf format in this page.

The subject HS8251 Technical English is for semester 2 of the Anna University.

As students requests the HS8251 Notes we have provided the Notes.

HS8251 Notes Text Books:

Board of editors. Fluency in English A Course book for Engineering and Technology. Orient Blackswan, Hyderabad: 2016

Sudharshana.N.P and Saveetha.  C.  English for  Technical  Communication.  Cambridge University Press: New Delhi, 2016

HS8251 Notes References:

  1. Raman, Meenakshi and Sharma, Sangeetha- Technical Communication Principles and Practice.Oxford University Press: New Delhi,2014.
  2. Kumar, Suresh. E. Engineering English. Orient Blackswan: Hyderabad,2015
  3. Booth-L. Diana, Project Work, Oxford University Press, Oxford: 2014.
  4. Grussendorf, Marion, English for Presentations, Oxford University Press, Oxford: 2007
  5. Means, L. Thomas and Elaine Langlois, English & Communication For Colleges.

Students can be asked to read Tagore, Chetan Bhagat and for supplementary reading.

Subject Name Technical English
Subject Code HS8251
Regulation 2017
Semester 2

Download HS8251 Notes Technical English Click Here

HS8251 Syllabus TECHNICAL ENGLISH


HS8251 Important questions TECHNICAL ENGLISH


HS8251 question bank TECHNICAL ENGLISH


 

Other links

Civil Engineering Subjects for regulation 2017


Mechanical Engineering Subjects for regulation 2017


Electrical and Electronics Engineering (EEE) Subjects for regulation 2017


Electronics and Communication Engineering (ECE) Subjects for regulation 2017


Computer Science and Engineering (CSE) Subjects for regulation 2017


Information Technology (IT) Subjects for regulation 2017


MA8251 Engineering Mathematics 2 Syllabus and notes click here


BE8251 Basic Electrical and Electronics Engineering click here


GE8291 Environmental Science and Engineering syllabus click here


GE8292 Engineering Mechanics Syllabus and notes click here


GE8261 Engineering Practices Laboratory syllabus click here


CE8211 Computer Aided Building Drawing syllabus click here


PH8201 Physics For Civil Engineering notes click here


 

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news

Neuralink

Neuralink

Neuralink Origin:

In 2015 professor Pedram Mohseni and Rudolph J. Nudo started a startup called neuralink.

These researchers had developed a device that can help people suffering from brain injury.

When they were looking for investors no one shows any interest on their project. In 2016 Elon musk bought this startup.

In 2017 Elon musk announces that he is going to start a new venture that interface human brain and computer.

Neuralink Elon musk

Goal of Neuralink:

The main goal of neuralink is to connect human intelligence with machine.

According to Elon AI (Artificial Intelligence) is the biggest threat for humans.

As AI is been advancing rapidly it is becoming too smart than human day by day.

But neuralink can help to override AI by linking human brain and machine.

Musk has been calling this technology as neural lace.

Neural lace:

Neural lace is a thin mesh injected into the skull which monitors the function of the brain and it will be wirelessly transfer data to a computer.

So far we don’t know how much does technology is developed.

As far as it is informed neural lace will help a human to upload and download data directly from a computer like in a science fiction movies.

Until now neural lace is been tested on live mouse. Researchers have found little negative side effects with in the mouse.

More than this it is just a beginning for a huge invention in the industry.

Application of neuralink:

The medical application of neuralink is to help the disabled and persons suffering from brain injuries such as alzheimers, parkinsons, seizures.

Others opinion 

Scientists says that with today’s technology we will not be able to download information into our brain in a day and become a Einstein.

And in the beginning it is a risk for human to get brain surgery with current technology.

But Elon musk is very confident that neuralink will be a the solution to beat Artificial intelligence.

Career option in Neuralink:

The company is developing ultra high band width interface between brain and computer machine. They are looking for engineers and scientists and the job is for full time in San Francisco.

For further details visit Click here

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BE8251 Notes r2017 notes

ADDER & FLIP FLOP

ADDER & FLIP FLOP

ADDER & FLIP-FLOP

Adder

There are two adder half adder, full adder

Half Adder

Half adder is a circuit that will add two bits & produce a sum & a carry bit. It needs two input bits & two output bits.

Ex-OR gate will only produce an output “1” when “EITHER” input is at logic “1”, so we need an additional output to produce a carry output, “1” when “BOTH” inputs “A” and “B” are at logic “1” and a standard AND Gate fits the bill nicely.

By combining the Ex-OR gate with the AND gate results in a simple digital binary adder circuit known commonly as the “Half Adder” circuit.

 Full Adder

A half adder has only two inputs & there is no provision to add a carry coming from the lower order bits when multi addition is performed.

For this purpose, a full adder is designed.

The 1-bit Full Adder circuit is basically two half adders connected together and consists of three Ex-OR gates, two AND gates and an OR gate, six logic gates in total.

The truth table for the full adder includes an additional column to take into account the Carry-in input as well as the summed output and carry-output.

Figure: Logic diagram of a Full adder using two Half Adders

Table: Truth Table for Full Adder

FLIP FLOP

 RS Flip Flop

RS Flip Flop have two inputs, S and R. S is called set and R is called reset.

The S input is used to produce HIGH on Q ( i.e. store binary 1 in flip-flop).

The R input is used to produce LOW on Q (i.e. store binary 0 in flip-flop). Q’ is Q complementary output, so it always holds the opposite value of Q.

The output of the S-R Flip Flop depends on current as well as previous inputs or state, and its state (value stored) can change as soon as its inputs change.

The circuit and the truth table of RS Flip Flop is shown below.

The operation has to be analyzed with the 4 inputs combinations together with the 2 possible previous states.

When S = 0 and R = 0: If we assume Q = 1 and Q’ = 0 as initial condition, then output Q after input is applied would be Q = (R + Q’)’ = 1 and Q’ = (S + Q)’ = 0.

Assuming Q = 0 and Q’ = 1 as initial condition, then output Q after the input applied would be Q = (R + Q’)’ = 0 and Q’ = (S + Q)’ = 1.

So it is clear that when both S and R inputs are LOW, the output is retained as before the application of inputs. (i.e. there is no state change).

When S = 1 and R = 0: If we assume Q = 1 and Q’ = 0 as initial condition, then output Q after input is applied would be Q = (R + Q’)’ = 1 and Q’ = (S + Q)’ = 0.

Assuming Q = 0 and Q’ = 1 as initial condition, then output Q after the input applied would be Q = (R + Q’)’ = 1 and Q’ = (S + Q)’ = 0. So in simple words when S is HIGH and R is LOW, output Q is HIGH.

When S = 0 and R = 1: If we assume Q = 1 and Q’ = 0 as initial condition, then output Q after input is applied would be Q = (R + Q’)’ = 0 and Q’ = (S + Q)’ = 1.

Assuming Q = 0 and Q’ = 1 as initial condition, then output Q after the input applied would be Q = (R + Q’)’ = 0 and Q’ = (S + Q)’ = 1.

So in simple words when S is LOW and R is HIGH, output Q is LOW.

When S = 1 and R =1 : No matter what state Q and Q’ are in, application of 1 at input of NOR gate always results in 0 at output of NOR gate, which results in both Q and Q’ set to LOW (i.e. Q = Q’). LOW in both the outputs basically is wrong, so this case is invalid.

It is possible to construct the RS Flip Flop using NAND gates (of course as seen in Logic gates section).

The only difference is that NAND is NOR gate dual form (Did I say that in Logic gates section?).

So in this case the R = 0 and S = 0 case becomes the invalid case. The circuit and Truth table of RS Flip Flop using NAND is shown below.

If you look closely, there is no control signal, so this kind of Flip Flopes or flip-flops are called asynchronous logic elements.

Since all the sequential circuits are built around the RS Flip Flop, we will concentrate on synchronous circuits and not on asynchronous circuits.

RS Flip Flop with Clock

We have seen this circuit earlier with two possible input configurations: one with level sensitive input and one with edge sensitive input.

The circuit below shows the level sensitive RS Flip Flop. Control signal “Enable” E is used to gate the input S and R to the RS Flip Flop.

When Enable E is HIGH, both the AND gates act as buffers and thus R and S appears at the RS Flip Flop input and it functions like a normal RS Flip Flop.

When Enable E is LOW, it drives LOW to both inputs of RS Flip Flop. As we saw in previous page, when both inputs of a NOR Flip Flop are low, values are retained (i.e. the output does not change).

Set up and Hold time

For synchronous flip-flops, we have special requirements for the inputs with respect to clock signal input. They are

Setup Time: Minimum time period during which data must be stable before the clock makes a valid transition.

For example, for a posedge triggered flip-flop, with a setup time of 2 ns, Input Data (i.e. R and S in the case of RS flip-flop) should be stable for at least 2 ns before clock makes transition from 0 to 1.

Hold Time: Minimum time period during which data must be stable after the clock has made a valid transition.

For example, for a posed triggered flip-flop, with a hold time of 1 ns. Input Data (i.e. R and S in the case of RS flip-flop) should be stable for at least 1 ns after clock has made transition from 0 to 1.

If data makes transition within this setup window and before the hold window, then the flip-flop output is not predictable, and flip-flop enters what is known as meta stable state.

In this state flip-flop output oscillates between 0 and 1.

It takes some time for the flip-flop to settle down.

The whole process is called Meta stability.

You could refer to tidbits section to know more information on this topic.

The waveform below shows input S (R is not shown), and CLK and output Q (Q’ is not shown) for a SR posed flip-flop.

Figure: Waveform for S-R and CLK

D Flip Flop

The RS Flip Flop seen earlier contains ambiguous state; to eliminate this condition we can ensure that S and R are never equal.

This is done by connecting S and R together with an inverter.

Thus we have D Flip Flop: the same as the RS Flip Flop, with the only difference that there is only one input, instead of two (R and S).

This input is called D or Data input. D Flip Flop is called D transparent Flip Flop for the reasons explained earlier.

Delay flip-flop or delay latch is another name used. Below is the truth table and circuit of D Flip Flop.

In real world designs (ASIC/FPGA Designs) only D latches/Flip-Flops are used.

Figure 2.12: D Flip Flop with Edge Sensitive and Level sensitive

Table: Truth table for D Flip Flop

Below is the D Flip Flop waveform, which is similar to the RS Flip Flop one, but with R removed.

Figure: D Flip Flop waveform

JK Flip Flop

The ambiguous state output in the RS Flip Flop was eliminated in the D Flip Flop by joining the inputs with an inverter.

But the D Flip Flop has a single input. JK Flip Flop is similar to RS Flip Flop in that it has 2 inputs J and K as shown Figurer below.

The ambiguous state has been eliminated here: when both inputs are high, output toggles.

The only difference we see here is output feedback to inputs, which is not there in the RS Flip Flop.

T Flip Flop

When the two inputs of JK Flip-Flop are shorted, a T Flip-Flop is formed. It is called T Flip-Flop as, when input is held HIGH, output toggles.

 JK Master Slave Flip-Flop

All sequential circuits that we have seen in the last few pages have a problem (All level sensitive sequential circuits have this problem).

Before the enable input changes state from HIGH to LOW (assuming HIGH is ON and LOW is OFF state), if inputs changes, then another state transition occurs for the same enable pulse.

This sort of multiple transition problem is called racing.

If we make the sequential element sensitive to edges, instead of levels, we can overcome this problem, as input is evaluated only during enable/clock edges.

Figure: JK Master Slave Flip-Flop

In the Figure above there are two Flip Flop, the first Flip-Flop on the left is called master Flip Flop and the one on the right is called slave Flip Flop.

Master Flip Flop is positively clocked and slave Flip Flop is negatively clocked.

Flip Flop

For more details about ADDER Click here

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Other links 

Construction of DC GENERATOR

Bipolar Junction Transistor(BJT)

Binary Number System and Conversion

Hexadecimal Numbers

ASCII Character Encoding

Logic Gates

Boolean Algebra

 

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BE8251 Notes r2017 notes

BOOLEAN ALGEBRA

BOOLEAN ALGEBRA

Boolean algebra is an algebraic structure defined by a set of elements, B, together with two binary operators, + and., provider that the following postulates are satisfied.

Commutative Law

(a) A+B = B+A

(b) A B = BA

Associative Law

(a) (A+B) +C = A+ (B+C)

(b) (A B) C = A (B C)

Distributive Law

(a)  A (B +C) = A B + AC

(b) A + (B C) = (A +B) (A+C)

Identity Law

(a)  A+A =A

(b) A A =A

Negative Law

(a)  (A’) =A’

(b) (A’’) = A

Redundant Law

(a)  A+AB=A

(b) A (A +B) =A

Null Law

(a)0 + A = A

(b) 1 A = A

(c) 1 + A = 1

(d) 0 A = 0

Double Negation Law

(a)  A’ +A=1

(b) A’ A=0

Absorption Law

(a)  A+A’B =A+B

(b) A (A’ + B) =AB

De Morgan’s Theorem

(a)  (A+B)’ = A’ B’

(b) (AB)’ = A’+B’

Example 1:

Using theorems,

A + A’ B = A l + A’ B

= A (l + B) + A’B

=A + AB + A’B

=A + B (A + A’)

= A + B

Using Truth Table

Verification Of De Morgan’s Theorems:

  • De Morgan’s First Theorem states:

The complement of a product of variables is equal to the sum of the complements of the individual variables

  • De Morgan’s Second Theorem states:

The complement of sum of variables is equal to the product of the complements of the dividable variables

BOOLEAN ALGEBRA

For more details about BOOLEAN ALGEBRA Click here

To see other topics in Basic Electrical and Electronics Engineering Click here

Click Here to Download the pdf of this topic BOOLEAN ALGEBRA

Other links 

Construction of DC GENERATOR

Bipolar Junction Transistor(BJT)

Binary Number System and Conversion

Hexadecimal Numbers

ASCII Character Encoding

Logic Gates

Adder & Flip Flop

Categories
BE8251 Notes

LOGIC GATES

LOGIC GATES

All digital systems are made from a few basic digital circuits that we call logic gates.

These circuits perform the basic logic functions that we will describe in this session.

The physical realization of these logic gates has changed over the years from mechanical relays to electronic vacuum tubes to transistors to integrated circuits containing thousands of transistors.

In this appendix you will learn:

Definitions of the basic gates in terms of truth tables and logic equations DeMorgan’s Theorem

How gates defined in terms of positive and negative logic are related To use multiple-input gates

How to perform a sum of products and a product of sums design from a truth table specification

The Three Basic Logic Gates

Much of a computer’s hardware is comprised of digital logic circuits.

Digital logic circuits are built from just a handful of primitive elements, called logic gates, combined in various ways.

In a digital logic circuit, only two values may be present.

The values may be −5 and + 5 volts Or the values may be 0.5 and 3.5 volts Or the values may be you get the picture.

To allow consideration of all of these possibilities, we will say that digital logic circuits allow the presence of two logical values: 0 and 1.

So, signals in a digital logic circuit take on the values of 0 or 1.

Logic gates are devices which compute functions of these binary signals.

AND Gate

Consider the circuit below which consists of a battery, a light, and two switches in series:

When will the light turn on? It should be clear that the light will turn on only if both switch S1 and switch S2 are shut.

It is quite likely that you encounter the and operation in some shape or form hundreds of times each day.

Consider the simple action of withdrawing funds from your checking account at an ATM.

You will only be able to complete the transaction if you have a checking account and you have money in it.

The ATM will only permit the transaction if you have your ATM card and you enter your correct 4-digit PIN.

To enter the correct PIN, you have to enter the first digit correctly and enter the second digit correctly and enter the third digit correctly and enter the fourth digit correctly.

Returning to the circuit above, we can represent the light’s operation using a table:

The switch is a binary device: it can be open or closed.

Let’s represent these two states as 0 and 1.

Likewise, the light is a binary device with two states: off and on, which we will represent as 0 and 1.

Rewriting the table above with this notation, we have:

This table, which displays the output for all possible combinations of the input, is termed the truth table for the AND operation.

In a computer, this and functionality is implemented with a circuit called an AND gate.

The simplest AND gate has two inputs and one output and is represented pictorially by the symbol:

where the inputs have been labeled a and b, and the output has been labeled c.

If both inputs are 1 then the output is 1. Otherwise, the output is 0.

We represent the and operation by using either the multiplication symbol (i.e., “  “) or by writing the inputs together.

Thus, for the AND gate shown above, we would write the output c as c = a b or as c = ab.

This would be pronounced: “c = and b.”

The truth table for the AND gate is shown below. The output c = ab is equal to 1 if and only if (iff) a is 1 and b is 1.

Otherwise, the output is 0.

AND gates can have more than one input (however, an AND gate always has just a single output).

Let’s consider a three-input AND gate:

OR Gate

Now consider the circuit shown below, that has 2 switches in parallel.

It is evident that the light will turn on when either switch S1 is shut or switch S2 is shut or both are shut.

It is quite likely that you encounter the or operation in some shape or form hundreds of times each day.

Consider the simple action of sitting on your couch at home at two in the morning studying for your Digital Logic class.

Your phone will ring if you get a call from Alice or from Bob.

Your home’s security alarm will go off if the front door opens or the back door opens.

You will drink a cup of coffee if you are drowsy or you are thirsty.

We can represent the light’s operation using a table

Changing the words open and off to 0 and the words shut and on to 1 and the table becomes:

This is the truth table for the OR operation.

This or functionality is implemented with a circuit called an OR gate.

The simplest OR gate has two inputs and one output and is represented pictorially by the symbol:

If either or both inputs are 1, the output is 1.

Otherwise, the output is 0.

We represent the or operation by using the addition symbol.

Thus, for the OR gate above, we would write the output c as c = a + b. This would be pronounced: “c = a or b.”

The truth table for the OR gate is shown below. The output is 1 if a is 1 or b is 1; otherwise, the output is 0.

NOT Gate

The last of our basic logic gates is the NOT gate.

The NOT gate always has one input and one output. If the input is 1, the output is 0.

If the input is 0, the output is 1. This operation— chaging the value of the binary input—is called complementation, negation or inversion.

The mathematical symbol for negation is an apostrophe.

If the input to a NOT gate is P, the output, termed the complement, is denoted as P’.

The pictorial symbol for a NOT gate is intended to depict an amplifier followed by a bubble, shown below.

Sometimes the NOT operation is represented by just the bubble, without the amplifier.

The truth table for the NOT gate is shown below:

Three New Gates

Three new gates, NAND, NOR, and Exclusive-OR, can be formed from our three basic gates: NOT, AND, and OR.

NAND Gate

The logic symbol for a NAND gate is like an AND gate with a small circle (or bubble) on the output.we see that the output of a NAND gate is 0 (low) only if both inputs are 1 (high) .

The NAND gate is equivalent to an AND gate followed by an inverter (NOT-AND).

NOR Gate

The logic symbol for a NOR gate is like an OR gate with a small circle (or bubble) on the output.

From the truth table .we see that the output of a NOR gate is 1 (high) only if both inputs are 0 (low).

The NOR gate is equivalent to an OR gate followed by an inverter (NOT-OR), as shown by the two truth tables.

Exclusive OR Gate

The XOR gate logic symbol is like an OR gate symbol with an extra curved vertical line on the input.

From the truth table .we see that the output Z of an XOR gate is 1 (true or high) if either input, X or Y, is 1 (true or high), but not both.

The output Z will be zero if both X and Y are the same (either both 1 or both 0).

The equation for the XOR gate is given as Z = X ^ Y. In this book we will use the symbol ^ as the XOR operator.

Sometimes the symbol or the dollar sign $ is used to denote Exclusive-OR.

We will use the symbol ^ because that is the symbol recognized by the Verilog software used to program a CPLD.

truth tables and logic equations DeMorgan's Theorem

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BE8251 Notes

ASCII Character Encoding

ASCII Character Encoding

ASCII Character Encoding the name ASCII is an acronym for: American Standard Code for Information Interchange.

It is a character encoding standard developed several decades ago to provide a standard way for digital machines to encode characters.

The ASCII code provides a mechanism for encoding alphabetic characters, numeric digits, and punctuation marks for use in representing text and numbers written using the Roman alphabet.

As originally designed, it was a seven bit code.

The seven bits allow the representation of 128 unique characters.

All of the alphabet, numeric digits and standard English punctuation marks are encoded.

The ASCII standard was later extended to an eight bit code (which allows 256 unique code patterns) and various additional symbols were added, including characters with diacritical marks (such as accents) used in European languages, which don’t appear in English.

There are also numerous non-standard extensions to ASCII giving different encoding for the upper 128 character codes than the standard.

For example, The character set encoded into the display card for the original IBM PC had a non-standard encoding for the upper character set.

This is a non-standard extension that is in very wide spread use, and could be considered a standard in itself.

Some important things to points about ASCII code:

The numeric digits, 0-9, are encoded in sequence starting at 30h

The upper case alphabetic characters are sequential beginning at 41h The lower case alphabetic characters are sequential beginning at 61h

The first 32 characters (codes 0-1Fh) and 7Fh are control characters.

They do not have a standard symbol (glyph) associated with them. They are used for carriage control, and protocol purposes.

The include 0Dh (CR or carriage return), 0Ah (LF or line feed), 0Ch (FF or form feed), 08h (BS or backspace).

Most keyboards generate the control characters by holding down a control key (CTRL) and simultaneously pressing an alphabetic character key.

The control code will have the same value as the lower five bits of the alphabetic key pressed.

So, for example, the control character 0Dh is carriage return. It can be generated by pressing CTRL-M.

To get the full 32 control characters a few at the upper end of the range are generated by pressing CTRL and a punctuation key in combination.

For example, the ESC (escape) character is generated by pressing CTRL-[ (left square bracket).

Conversions Between Upper and Lower Case ASCII Letters

ASCII code chart that the uppercase letters start at 41h and that the lower case letters begin at 61h.

In each case, the rest of the letters are consecutive and in alphabetic order.

The difference between 41h and 61h is 20h. Therefore the conversion between upper and lower case involves either adding or subtracting 20h to the character code.

To convert a lower case letter to upper case, subtract 20h, and conversely to convert upper case to lower case, add 20h.

It is important to note that you need to first ensure that you do in fact have an alphabetic character before performing the addition or subtraction.

Ordinarily, a check should be made that the character is in the range 41h–5Ah for upper case or 61h-7Ah for lower case.

Conversion Between ASCII and BCD

ASCII code chart that the numeric characters are in the range 30h-39h.

Conversion between an ASCII encoded digit and an unpacked BCD digit can be accomplished by adding or subtracting 30h.

Subtract 30h from an ASCII digit to get BCD, or add 30h to a BCD digit to get ASCII.

Again, as with upper and lower case conversion for alphabetic characters, it is necessary to ensure that the character is in fact a numeric digit before performing the subtraction.

The digit characters are in the range 30h-39h.

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Construction of DC GENERATOR

Bipolar Junction Transistor(BJT)

Binary Number System and Conversion

Hexadecimal Numbers

Logic Gates

Boolean Algebra

Adder & Flip Flop