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Half adder is a circuit that will add two bits & produce a sum & a carry bit. It needs two input bits & two output bits.

Ex-OR gate will only produce an output “1” when “EITHER” input is at logic “1”, so we need an additional output to produce a carry output, “1” when “BOTH” inputs “A” and “B” are at logic “1” and a standard AND Gate fits the bill nicely.

By combining the Ex-OR gate with the AND gate results in a simple digital binary adder circuit known commonly as the “Half Adder” circuit.

A half adder has only two inputs & there is no provision to add a carry coming from the lower order bits when multi addition is performed.

For this purpose, a full adder is designed.

The 1-bit Full Adder circuit is basically two half adders connected together and consists of three Ex-OR gates, two AND gates and an OR gate, six logic gates in total.

The truth table for the full adder includes an additional column to take into account the Carry-in input as well as the summed output and carry-output.

Table: Truth Table for Full Adder

## FLIP FLOP

### RS Flip Flop

RS Flip Flop have two inputs, S and R. S is called set and R is called reset.

The S input is used to produce HIGH on Q ( i.e. store binary 1 in flip-flop).

The R input is used to produce LOW on Q (i.e. store binary 0 in flip-flop). Q’ is Q complementary output, so it always holds the opposite value of Q.

The output of the S-R Flip Flop depends on current as well as previous inputs or state, and its state (value stored) can change as soon as its inputs change.

The circuit and the truth table of RS Flip Flop is shown below.

The operation has to be analyzed with the 4 inputs combinations together with the 2 possible previous states.

When S = 0 and R = 0: If we assume Q = 1 and Q’ = 0 as initial condition, then output Q after input is applied would be Q = (R + Q’)’ = 1 and Q’ = (S + Q)’ = 0.

Assuming Q = 0 and Q’ = 1 as initial condition, then output Q after the input applied would be Q = (R + Q’)’ = 0 and Q’ = (S + Q)’ = 1.

So it is clear that when both S and R inputs are LOW, the output is retained as before the application of inputs. (i.e. there is no state change).

When S = 1 and R = 0: If we assume Q = 1 and Q’ = 0 as initial condition, then output Q after input is applied would be Q = (R + Q’)’ = 1 and Q’ = (S + Q)’ = 0.

Assuming Q = 0 and Q’ = 1 as initial condition, then output Q after the input applied would be Q = (R + Q’)’ = 1 and Q’ = (S + Q)’ = 0. So in simple words when S is HIGH and R is LOW, output Q is HIGH.

When S = 0 and R = 1: If we assume Q = 1 and Q’ = 0 as initial condition, then output Q after input is applied would be Q = (R + Q’)’ = 0 and Q’ = (S + Q)’ = 1.

Assuming Q = 0 and Q’ = 1 as initial condition, then output Q after the input applied would be Q = (R + Q’)’ = 0 and Q’ = (S + Q)’ = 1.

So in simple words when S is LOW and R is HIGH, output Q is LOW.

When S = 1 and R =1 : No matter what state Q and Q’ are in, application of 1 at input of NOR gate always results in 0 at output of NOR gate, which results in both Q and Q’ set to LOW (i.e. Q = Q’). LOW in both the outputs basically is wrong, so this case is invalid.

It is possible to construct the RS Flip Flop using NAND gates (of course as seen in Logic gates section).

The only difference is that NAND is NOR gate dual form (Did I say that in Logic gates section?).

So in this case the R = 0 and S = 0 case becomes the invalid case. The circuit and Truth table of RS Flip Flop using NAND is shown below.

If you look closely, there is no control signal, so this kind of Flip Flopes or flip-flops are called asynchronous logic elements.

Since all the sequential circuits are built around the RS Flip Flop, we will concentrate on synchronous circuits and not on asynchronous circuits.

### RS Flip Flop with Clock

We have seen this circuit earlier with two possible input configurations: one with level sensitive input and one with edge sensitive input.

The circuit below shows the level sensitive RS Flip Flop. Control signal “Enable” E is used to gate the input S and R to the RS Flip Flop.

When Enable E is HIGH, both the AND gates act as buffers and thus R and S appears at the RS Flip Flop input and it functions like a normal RS Flip Flop.

When Enable E is LOW, it drives LOW to both inputs of RS Flip Flop. As we saw in previous page, when both inputs of a NOR Flip Flop are low, values are retained (i.e. the output does not change).

### Set up and Hold time

For synchronous flip-flops, we have special requirements for the inputs with respect to clock signal input. They are

Setup Time: Minimum time period during which data must be stable before the clock makes a valid transition.

For example, for a posedge triggered flip-flop, with a setup time of 2 ns, Input Data (i.e. R and S in the case of RS flip-flop) should be stable for at least 2 ns before clock makes transition from 0 to 1.

Hold Time: Minimum time period during which data must be stable after the clock has made a valid transition.

For example, for a posed triggered flip-flop, with a hold time of 1 ns. Input Data (i.e. R and S in the case of RS flip-flop) should be stable for at least 1 ns after clock has made transition from 0 to 1.

If data makes transition within this setup window and before the hold window, then the flip-flop output is not predictable, and flip-flop enters what is known as meta stable state.

In this state flip-flop output oscillates between 0 and 1.

It takes some time for the flip-flop to settle down.

The whole process is called Meta stability.

You could refer to tidbits section to know more information on this topic.

The waveform below shows input S (R is not shown), and CLK and output Q (Q’ is not shown) for a SR posed flip-flop.

Figure: Waveform for S-R and CLK

### D Flip Flop

The RS Flip Flop seen earlier contains ambiguous state; to eliminate this condition we can ensure that S and R are never equal.

This is done by connecting S and R together with an inverter.

Thus we have D Flip Flop: the same as the RS Flip Flop, with the only difference that there is only one input, instead of two (R and S).

This input is called D or Data input. D Flip Flop is called D transparent Flip Flop for the reasons explained earlier.

Delay flip-flop or delay latch is another name used. Below is the truth table and circuit of D Flip Flop.

In real world designs (ASIC/FPGA Designs) only D latches/Flip-Flops are used.

Figure 2.12: D Flip Flop with Edge Sensitive and Level sensitive

Table: Truth table for D Flip Flop

Below is the D Flip Flop waveform, which is similar to the RS Flip Flop one, but with R removed.

Figure: D Flip Flop waveform

### JK Flip Flop

The ambiguous state output in the RS Flip Flop was eliminated in the D Flip Flop by joining the inputs with an inverter.

But the D Flip Flop has a single input. JK Flip Flop is similar to RS Flip Flop in that it has 2 inputs J and K as shown Figurer below.

The ambiguous state has been eliminated here: when both inputs are high, output toggles.

The only difference we see here is output feedback to inputs, which is not there in the RS Flip Flop.

### T Flip Flop

When the two inputs of JK Flip-Flop are shorted, a T Flip-Flop is formed. It is called T Flip-Flop as, when input is held HIGH, output toggles.

### JK Master Slave Flip-Flop

All sequential circuits that we have seen in the last few pages have a problem (All level sensitive sequential circuits have this problem).

Before the enable input changes state from HIGH to LOW (assuming HIGH is ON and LOW is OFF state), if inputs changes, then another state transition occurs for the same enable pulse.

This sort of multiple transition problem is called racing.

If we make the sequential element sensitive to edges, instead of levels, we can overcome this problem, as input is evaluated only during enable/clock edges.

Figure: JK Master Slave Flip-Flop

In the Figure above there are two Flip Flop, the first Flip-Flop on the left is called master Flip Flop and the one on the right is called slave Flip Flop.

Master Flip Flop is positively clocked and slave Flip Flop is negatively clocked.

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# BOOLEAN ALGEBRA

Boolean algebra is an algebraic structure defined by a set of elements, B, together with two binary operators, + and., provider that the following postulates are satisfied.

## Commutative Law

(a) A+B = B+A

(b) A B = BA

### Associative Law

(a) (A+B) +C = A+ (B+C)

(b) (A B) C = A (B C)

### Distributive Law

(a)  A (B +C) = A B + AC

(b) A + (B C) = (A +B) (A+C)

(a)  A+A =A

(b) A A =A

(a)  (A’) =A’

(b) (A’’) = A

(a)  A+AB=A

(b) A (A +B) =A

(a)0 + A = A

(b) 1 A = A

(c) 1 + A = 1

(d) 0 A = 0

(a)  A’ +A=1

(b) A’ A=0

### Absorption Law

(a)  A+A’B =A+B

(b) A (A’ + B) =AB

### De Morgan’s Theorem

(a)  (A+B)’ = A’ B’

(b) (AB)’ = A’+B’

Example 1:

Using theorems,

A + A’ B = A l + A’ B

= A (l + B) + A’B

=A + AB + A’B

=A + B (A + A’)

= A + B

Using Truth Table

### Verification Of De Morgan’s Theorems:

• De Morgan’s First Theorem states:

The complement of a product of variables is equal to the sum of the complements of the individual variables

• De Morgan’s Second Theorem states:

The complement of sum of variables is equal to the product of the complements of the dividable variables

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# LOGIC GATES

All digital systems are made from a few basic digital circuits that we call logic gates.

These circuits perform the basic logic functions that we will describe in this session.

The physical realization of these logic gates has changed over the years from mechanical relays to electronic vacuum tubes to transistors to integrated circuits containing thousands of transistors.

In this appendix you will learn:

Definitions of the basic gates in terms of truth tables and logic equations DeMorgan’s Theorem

How gates defined in terms of positive and negative logic are related To use multiple-input gates

How to perform a sum of products and a product of sums design from a truth table specification

## The Three Basic Logic Gates

Much of a computer’s hardware is comprised of digital logic circuits.

Digital logic circuits are built from just a handful of primitive elements, called logic gates, combined in various ways.

In a digital logic circuit, only two values may be present.

The values may be −5 and + 5 volts Or the values may be 0.5 and 3.5 volts Or the values may be you get the picture.

To allow consideration of all of these possibilities, we will say that digital logic circuits allow the presence of two logical values: 0 and 1.

So, signals in a digital logic circuit take on the values of 0 or 1.

Logic gates are devices which compute functions of these binary signals.

### AND Gate

Consider the circuit below which consists of a battery, a light, and two switches in series:

When will the light turn on? It should be clear that the light will turn on only if both switch S1 and switch S2 are shut.

It is quite likely that you encounter the and operation in some shape or form hundreds of times each day.

Consider the simple action of withdrawing funds from your checking account at an ATM.

You will only be able to complete the transaction if you have a checking account and you have money in it.

The ATM will only permit the transaction if you have your ATM card and you enter your correct 4-digit PIN.

To enter the correct PIN, you have to enter the first digit correctly and enter the second digit correctly and enter the third digit correctly and enter the fourth digit correctly.

Returning to the circuit above, we can represent the light’s operation using a table:

The switch is a binary device: it can be open or closed.

Let’s represent these two states as 0 and 1.

Likewise, the light is a binary device with two states: off and on, which we will represent as 0 and 1.

Rewriting the table above with this notation, we have:

This table, which displays the output for all possible combinations of the input, is termed the truth table for the AND operation.

In a computer, this and functionality is implemented with a circuit called an AND gate.

The simplest AND gate has two inputs and one output and is represented pictorially by the symbol:

where the inputs have been labeled a and b, and the output has been labeled c.

If both inputs are 1 then the output is 1. Otherwise, the output is 0.

We represent the and operation by using either the multiplication symbol (i.e., “  “) or by writing the inputs together.

Thus, for the AND gate shown above, we would write the output c as c = a b or as c = ab.

This would be pronounced: “c = and b.”

The truth table for the AND gate is shown below. The output c = ab is equal to 1 if and only if (iff) a is 1 and b is 1.

Otherwise, the output is 0.

AND gates can have more than one input (however, an AND gate always has just a single output).

Let’s consider a three-input AND gate:

### OR Gate

Now consider the circuit shown below, that has 2 switches in parallel.

It is evident that the light will turn on when either switch S1 is shut or switch S2 is shut or both are shut.

It is quite likely that you encounter the or operation in some shape or form hundreds of times each day.

Consider the simple action of sitting on your couch at home at two in the morning studying for your Digital Logic class.

Your phone will ring if you get a call from Alice or from Bob.

Your home’s security alarm will go off if the front door opens or the back door opens.

You will drink a cup of coffee if you are drowsy or you are thirsty.

We can represent the light’s operation using a table

Changing the words open and off to 0 and the words shut and on to 1 and the table becomes:

This is the truth table for the OR operation.

This or functionality is implemented with a circuit called an OR gate.

The simplest OR gate has two inputs and one output and is represented pictorially by the symbol:

If either or both inputs are 1, the output is 1.

Otherwise, the output is 0.

We represent the or operation by using the addition symbol.

Thus, for the OR gate above, we would write the output c as c = a + b. This would be pronounced: “c = a or b.”

The truth table for the OR gate is shown below. The output is 1 if a is 1 or b is 1; otherwise, the output is 0.

### NOT Gate

The last of our basic logic gates is the NOT gate.

The NOT gate always has one input and one output. If the input is 1, the output is 0.

If the input is 0, the output is 1. This operation— chaging the value of the binary input—is called complementation, negation or inversion.

The mathematical symbol for negation is an apostrophe.

If the input to a NOT gate is P, the output, termed the complement, is denoted as P’.

The pictorial symbol for a NOT gate is intended to depict an amplifier followed by a bubble, shown below.

Sometimes the NOT operation is represented by just the bubble, without the amplifier.

The truth table for the NOT gate is shown below:

## Three New Gates

Three new gates, NAND, NOR, and Exclusive-OR, can be formed from our three basic gates: NOT, AND, and OR.

### NAND Gate

The logic symbol for a NAND gate is like an AND gate with a small circle (or bubble) on the output.we see that the output of a NAND gate is 0 (low) only if both inputs are 1 (high) .

The NAND gate is equivalent to an AND gate followed by an inverter (NOT-AND).

### NOR Gate

The logic symbol for a NOR gate is like an OR gate with a small circle (or bubble) on the output.

From the truth table .we see that the output of a NOR gate is 1 (high) only if both inputs are 0 (low).

The NOR gate is equivalent to an OR gate followed by an inverter (NOT-OR), as shown by the two truth tables.

### Exclusive OR Gate

The XOR gate logic symbol is like an OR gate symbol with an extra curved vertical line on the input.

From the truth table .we see that the output Z of an XOR gate is 1 (true or high) if either input, X or Y, is 1 (true or high), but not both.

The output Z will be zero if both X and Y are the same (either both 1 or both 0).

The equation for the XOR gate is given as Z = X ^ Y. In this book we will use the symbol ^ as the XOR operator.

Sometimes the symbol or the dollar sign \$ is used to denote Exclusive-OR.

We will use the symbol ^ because that is the symbol recognized by the Verilog software used to program a CPLD.

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# ASCII Character Encoding

ASCII Character Encoding the name ASCII is an acronym for: American Standard Code for Information Interchange.

It is a character encoding standard developed several decades ago to provide a standard way for digital machines to encode characters.

The ASCII code provides a mechanism for encoding alphabetic characters, numeric digits, and punctuation marks for use in representing text and numbers written using the Roman alphabet.

As originally designed, it was a seven bit code.

The seven bits allow the representation of 128 unique characters.

All of the alphabet, numeric digits and standard English punctuation marks are encoded.

The ASCII standard was later extended to an eight bit code (which allows 256 unique code patterns) and various additional symbols were added, including characters with diacritical marks (such as accents) used in European languages, which don’t appear in English.

There are also numerous non-standard extensions to ASCII giving different encoding for the upper 128 character codes than the standard.

For example, The character set encoded into the display card for the original IBM PC had a non-standard encoding for the upper character set.

This is a non-standard extension that is in very wide spread use, and could be considered a standard in itself.

Some important things to points about ASCII code:

The numeric digits, 0-9, are encoded in sequence starting at 30h

The upper case alphabetic characters are sequential beginning at 41h The lower case alphabetic characters are sequential beginning at 61h

The first 32 characters (codes 0-1Fh) and 7Fh are control characters.

They do not have a standard symbol (glyph) associated with them. They are used for carriage control, and protocol purposes.

The include 0Dh (CR or carriage return), 0Ah (LF or line feed), 0Ch (FF or form feed), 08h (BS or backspace).

Most keyboards generate the control characters by holding down a control key (CTRL) and simultaneously pressing an alphabetic character key.

The control code will have the same value as the lower five bits of the alphabetic key pressed.

So, for example, the control character 0Dh is carriage return. It can be generated by pressing CTRL-M.

To get the full 32 control characters a few at the upper end of the range are generated by pressing CTRL and a punctuation key in combination.

For example, the ESC (escape) character is generated by pressing CTRL-[ (left square bracket).

## Conversions Between Upper and Lower Case ASCII Letters

ASCII code chart that the uppercase letters start at 41h and that the lower case letters begin at 61h.

In each case, the rest of the letters are consecutive and in alphabetic order.

The difference between 41h and 61h is 20h. Therefore the conversion between upper and lower case involves either adding or subtracting 20h to the character code.

To convert a lower case letter to upper case, subtract 20h, and conversely to convert upper case to lower case, add 20h.

It is important to note that you need to first ensure that you do in fact have an alphabetic character before performing the addition or subtraction.

Ordinarily, a check should be made that the character is in the range 41h–5Ah for upper case or 61h-7Ah for lower case.

### Conversion Between ASCII and BCD

ASCII code chart that the numeric characters are in the range 30h-39h.

Conversion between an ASCII encoded digit and an unpacked BCD digit can be accomplished by adding or subtracting 30h.

Subtract 30h from an ASCII digit to get BCD, or add 30h to a BCD digit to get ASCII.

Again, as with upper and lower case conversion for alphabetic characters, it is necessary to ensure that the character is in fact a numeric digit before performing the subtraction.

The digit characters are in the range 30h-39h.

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In addition to binary, another number base that is commonly used in digital systems is base 16.

This number system is called hexadecimal, and each digit position represents a power of 16.

For any number base greater than ten, a problem occurs because there are more than ten symbols needed to represent the numerals for that number base.

It is customary in these cases to use the ten decimal numerals followed by the letters of the alphabet beginning with A to provide the needed numerals.

Since the hexadecimal system is base 16, there are sixteen numerals required.

The following are the hexadecimal numerals:

0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F

The following are some examples of hexadecimal numbers:

1016  4716  3FA16 A03F16

The reason for the common use of hexadecimal numbers is the relationship between the numbers 2 and 16.

Sixteen is a power of 2 (16 = 24).

Because of this relationship, four digits in a binary number can be represented with a single hexadecimal digit.

This makes conversion between binary and hexadecimal numbers very easy, and hexadecimal can be used to write large binary numbers with much fewer digits.

When working with large digital systems, such as computers, it is common to find binary numbers with 8, 16 and even 32 digits. Writing a 16 or 32 bit binary number would be quite tedious and error prone.

By using hexadecimal, the numbers can be written with fewer digits and much less likelihood of error.

To convert a binary number to hexadecimal, divide it into groups of four digits starting with the rightmost digit.

If the number of digits isn’t a multiple of 4, prefix the number with 0’s so that each group contains 4 digits.

For each four digit group, convert the 4 bit binary number into an equivalent hexadecimal digit.

See the Binary, BCD, and Hexadecimal Number Tables at the end of this document for the correspondence between 4 bit binary patterns and hexadecimal digits.

## Convert the binary number 10110101 to a hexadecimal number

To convert a hexadecimal number to a binary number, convert each hexadecimal digit into a group of 4 binary digits.

Convert the hex number 374F into binary

There are several ways in common use to specify that a given number is in hexadecimal representation rather than some other radix.

In cases where the context makes it absolutely clear that numbers are represented in hexadecimal, no indicator is used.

Written material where the context doesn’t make it clear what the radix is, the numeric subscript 16 following the hexadecimal number is used.

Programming languages, this method isn’t really feasible, so there are several conventions used depending on the language.

In the C and C++ languages, hexadecimal constants are represented with a ‘0x’ preceding the number, as in: 0x317F, or 0x1234, or 0xAF.

In assembler programming languages that follow the Intel style, a hexadecimal constant begins with a numeric character (so that the assembler can distinguish it from a variable name), a leading ‘0’ being used if necessary.

The letter ‘h’ is then suffixed onto the number to inform the assembler that it is a hexadecimal constant. In Intel style assembler format: 371Fh and 0FABCh are valid hexadecimal constants. Note that: A37h isn’t a valid hexadecimal constant.

It doesn’t begin with a numeric character, and so will be taken by the assembler as a variable name.

In assembler programming languages that follow the Motorola style, hexadecimal constants begin with a ‘\$’ character.

So in this case: \$371F or \$FABC or \$01 are valid hexadecimal constants.

### Binary Coded Decimal Numbers

Another number system that is encountered occasionally is Binary Coded Decimal.

In this system, numbers are represented in a decimal form, however each decimal digit is encoded using a four bit binary number.

The decimal number 136 would be represented in BCD as follows: 136 = 0001 0011 0110

1     3      6

Conversion of numbers between decimal and BCD is quite simple.

To convert from decimal to BCD, simply write down the four bit binary pattern for each decimal digit.

To convert from BCD to decimal, divide the number into groups of 4 bits and write down the corresponding decimal digit for each 4 bit group.

There are a couple of variations on the BCD representation, namely packed and unpacked.

An unpacked BCD number has only a single decimal digit stored in each data byte.

In this case, the decimal digit will be in the low four bits and the upper 4 bits of the byte will be 0.

In the packed BCD representation, two decimal digits are placed in each byte.

Generally, the high order bits of the data byte contain the more significant decimal digit.

The following is a 16 bit number encoded in packed BCD format:

01010110 10010011

This is converted to a decimal number as follows: 0101 0110 1001 0011

5 6 9 3 The value is 5693 decimal

The same number in unpacked BCD (requires 32 bits)

00000101 00000110 00001001 00000011

5          6            9            3

The use of BCD to represent numbers isn’t as common as binary in most computer systems, as it is not as space efficient.

In packed BCD, only 10 of the 16 possible bit patterns in each 4 bit unit are used. In unpacked BCD, only 10 of the 256 possible bit patterns in each byte are used.

A 16 bit quantity can represent the range 0-65535 in binary, 0-9999 in packed BCD and only 0-99 in unpacked BCD.

#### Fixed Precision and Overflow

we haven’t considered the maximum size of the number. We have assumed that as many bits are available as needed to represent the number.

In most computer systems, this isn’t the case. Numbers in computers are typically represented using a fixed number of bits.

These sizes are typically 8 bits, 16 bits, 32 bits, 64 bits and 80 bits.

These sizes are generally a multiple of 8, as most computer memories are organized on an 8 bit byte basis.

Numbers in which a specific number of bits are used to represent the value are called fixed precision numbers.

When a specific number of bits are used to represent a number, that determines the range of possible values that can be represented.

For example, there are 256 possible combinations of 8 bits, therefore an 8 bit number can represent 256 distinct numeric values and the range is typically considered to be 0-255.

Any number larger than 255 can’t be represented using 8 bits. Similarly, 16 bits allows a range of 0-65535.

When fixed precision numbers are used, (as they are in virtually all computer calculations) the concept of overflow must be considered.

An overflow occurs when the result of a calculation can’t be represented with the number of bits available.

For example when adding the two eight bit quantities: 150 + 170, the result is 320.

This is outside the range 0-255, and so the result can’t be represented using 8 bits.

The result has overflowed the available range.

When overflow occurs, the low order bits of the result will remain valid, but the high order bits will be lost.

This results in a value that is significantly smaller than the correct result.

When doing fixed precision arithmetic (which all computer arithmetic involves) it is necessary to be conscious of the possibility of overflow in the calculations.

##### Signed and Unsigned Numbers

we have only considered positive values for binary numbers.

When a fixed precision binary number is used to hold only positive values, it is said to be unsigned.

In this case, the range of positive values that can be represented is 0 — 2n-1, where n is the number of bits used.

It is also possible to represent signed (negative as well as positive) numbers in binary.

In this case, part of the total range of values is used to represent positive values, and the rest of the range is used to represent negative values.

There are several ways that signed numbers can be represented in binary, but the most common representation used today is called two’s complement.

The term two’s complement is somewhat ambiguous, in that it is used in two different ways.

First, as a representation, two’s complement is a way of interpreting and assigning meaning to a bit pattern contained in a fixed precision binary quantity.

Second, the term two’s complement is also used to refer to an operation that can be performed on the bits of a binary quantity.

As an operation, the two’s complement of a number is formed by inverting all of the bits and adding 1.

In a binary number being interpreted using the two’s complement representation, the high order bit of the number indicates the sign.

If the sign bit is 0, the number is positive, and if the sign bit is 1, the number is negative.

For positive numbers, the rest of the bits hold the true magnitude of the number.

For negative numbers, the lower order bits hold the complement (or bitwise inverse) of the magnitude of the number.

It is important to note that two’s complement representation can only be applied to fixed precision quantities, that is, quantities where there are a set number of bits.

Two’s complement representation is used because it reduces the complexity of the hardware in the arithmetic-logic unit of a computer’s CPU.

Using a two’s complement representation, all of the arithmetic operations can be performed by the same hardware whether the numbers are considered to be unsigned or signed.

The bit operations performed are identical, the difference comes from the interpretation of the bits.

The interpretation of the value will be different depending on whether the value is considered to be unsigned or signed.

Find the 2’s complement of the following 8 bit number

The 2’s complement of 00101001 is 11010111

Find the 2’s complement of the following 8 bit number 10110101

The 2’s complement of 10110101 is 01001011

The counting sequence for an eight bit binary value using 2’s complement representation appears as follows:

Counting up from 0, when 127 is reached, the next binary pattern in the sequence corresponds to -128.

The values jump from the greatest positive number to the greatest negative number, but that the sequence is as expected after that. (i.e. adding 1 to –128 yields –127, and so on.).

When the count has progressed to 0FFh (or the largest unsigned magnitude possible) the count wraps around to 0. (i.e. adding 1 to –1 yields 0).

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# BINARY NUMBER SYSTEM

The number system that you are familiar with, that you use every day, is the decimal number system, also commonly referred to as the base-10 system.

When you perform computations such as 3 + 2 = 5, or 21 – 7 = 14, you are using the decimal number system.

This system, which you likely learned in first or second grade, is ingrained into your subconscious; it’s the natural way that you think about numbers.

Evidence exists that Egyptians were using a decimal number system five thousand years ago.

The Roman numeral system, predominant for hundreds of years, was also a decimal number system (though organized differently from the Arabic base-10 number system that we are most familiar with).

Indeed, base-10 systems, in one form or another, have been the most widely used number systems ever since civilization started counting.

In dealing with the inner workings of a computer, though, you are going to have to learn to think in a different number system, the binary number system, also referred to as the base-2 system.

Consider a child counting a pile of pennies. He would begin: “One, two, three, …, eight, nine.”

Upon reaching nine, the next penny counted makes the total one single group of ten pennies.

He then keeps counting: “One group of ten pennies two groups of ten pennies three groups of ten pennies eight groups of ten pennies nine groups of ten pennies”.

Upon reaching nine groups of ten pennies plus nine additional pennies, the next penny counted makes the total thus far: one single group of one hundred pennies.

Upon completing the task, the child might find that he has three groups of one hundred pennies, five groups of ten pennies, and two pennies left over: 352 pennies.

More formally, the base-10 system is a positional system, where the rightmost digit is the ones position (the number of ones), the next digit to the left is the tens position (the number of groups of 10), the next digit to the left is the hundreds position (the number of groups of 100), and so forth.

The base-10 number system has 10 distinct symbols, or digits (0, 1, 2, 3,…8, 9).

In decimal notation, we write a number as a string of symbols, where each symbol is one of these ten digits, and to interpret a decimal number, we multiply each digit by the power of 10 associated with that digit’s position.

For example, consider the decimal number: 6349. This number is:

Consider: Computers are built from transistors, and an individual transistor can only be ON or OFF (two options).

Similarly, data storage devices can be optical or magnetic.

Optical storage devices store data in a specific location by controlling whether light is reflected off that location or is not reflected off that location (two options).

Likewise, magnetic storage devices store data in a specific location by magnetizing the particles in that location with a specific orientation.

We can have the north magnetic pole pointing in one direction, or the opposite direction (two options).

Computers can most readily use two symbols, and therefore a base-2 system, or binary number system, is most appropriate.

The base-10 number system has 10 distinct symbols: 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9.

The base-2 system has exactly two symbols: 0 and 1. The base-10 symbols are termed digits.

The base-2 symbols are termed binary digits, or bits for short. All base-10 numbers are built as strings of digits (such as 6349).

All binary numbers are built as strings of bits (such as 1101).

Just as we would say that the decimal number 12890 has five digits, we would say that the binary number 11001 is a five-bit number.

## The Binary Number System

Consider again the example of a child counting a pile of pennies, but this time in binary.

He would begin with the first penny: “1.”

The next penny counted makes the total one single group of two pennies. What number is this?

When the base-10 child reached nine (the highest symbol in his scheme), the next penny gave him “one group of ten”, denoted as 10, where the “1” indicated one collection of ten.

Similarly, when the base-2 child reaches one (the highest symbol in his scheme), the next penny gives him “one group of two”, denoted as 10, where the “1” indicates one collection of two.

Back to the base-2 child: The next penny makes one group of two pennies and one additional penny: “11.”

The next penny added makes two groups of two, which is one group of 4: “100.”

The “1” here indicates a collection of two groups of two, just as the “1” in the base-10 number 100 indicates ten groups of ten.

Upon completing the counting task, base -2 child might find that he has one group of four pennies, no groups of two pennies, and one penny left over: 101 pennies.

The child counting the same pile of pennies in base-10 would conclude that there were 5 pennies.

So, 5 in base-10 is equivalent to101 in base-2.

To avoid confusion when the base in use if not clear from the context, or when using multiple bases in a single expression, We append a subscript to the number to indicate the base, and write:

510 =1012

Just as with decimal notation, we write a binary number as a string of symbols, but now each symbol is a 0 or a 1.

To interpret a binary number, we multiply each digit by the power of 2 associated with that digit’s position.

For example, consider the binary number 1101. This number is:

Since binary numbers can only contain the two symbols 0 and 1, numbers such as 25 and 1114000 cannot be binary numbers.

We say that all data in a computer is stored in binary—that is, as 1’s and 0’s.

It is important to keep in mind that values of 0 and 1 are logical values, not the values of a physical quantity, such as a voltage.

The actual physical binary values used to store data internally within a computer might be, for instance, 5 volts and 0 volts, or perhaps 3.3 volts and 0.3 volts or perhaps reflection and no reflection.

The two values that are used to physically store data can differ within different portions of the same computer.

All that really matters is that there are two different symbols, so we will always refer to them as 0 and 1.

A string of eight bits (such as 11000110) is termed a byte.

A collection of four bits (such as 1011) is smaller than a byte, and is hence termed a nibble.

This is the sort of nerd-humor for which engineers are famous.

The idea of describing numbers using a positional system, as we have illustrated for base-10 and base-2, can be extended to any base. For example, the base-4 number 231 is:

## Converting Between Binary Numbers and Decimal Numbers

We humans about numbers using the decimal number system, whereas computers use the binary number system.

We need to be able to readily shift between the binary and decimal number representations.

### Converting a Binary Number to a Decimal Number

To convert a binary number to a decimal number, we simply write the binary number as a sum of powers of 2.

For example, to convert the binary number 1011 to a decimal number, we note that the rightmost position is the ones position and the bit value in this position is a 1.

So, this rightmost bit has the decimal value of 1⋅20.

The next position to the left is the twos position, and the bit value in this position is also a 1.

So, this next bit has the decimal value of 1⋅ 21.

The next position to the left is the fours position, and the bit value in this position is a 0.

The leftmost position is the eights position, and the bit value in this position is a 1.

So, this leftmost bit has the decimal value of 1⋅23.

Thus:

The binary number 110110 as a decimal number. Solution:

For example, to convert the binary number 10101 to decimal, we annotate the position values below the bit values:

Then we add the position values for those positions that have a bit value of 1: 16 + 4 + 1 = 21.

Thus 101012 = 2110

You should “memorize” the binary representations of the decimal digits 0 through 15 shown below.

You may be wondering about the leading zeros in the table above.

For example, the decimal number 5 is represented in the table as the binary number 0101.

We could have represented the binary equivalent of 5 as 101, 00101, 0000000101, or with any other number of leading zeros.

Sometimes, though, you will be given the size of a storage location.

When you are given the size of the storage location, include the leading zeros to show all bits in the storage location.

For example, if told to represent decimal 5 as an 8-bit binary number, your answer should be 00000101.

### Converting a Decimal Number to a Binary Number:

Method 2

The second method of converting a decimal number to a binary number entails repeatedly dividing the decimal number by 2, keeping track of the remainder at each step. To convert the decimal number x to binary:

Step 1. Divide x by 2 to obtain a quotient and remainder. The remainder will be 0 or 1.

Step 2. If the quotient is zero, you are finished: Proceed to Step 3. Otherwise, go back to Step 1, assigning x to be the value of the most-recent quotient from Step 1.

Step 3. The sequence of remainders forms the binary representation of the number.

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# BIPOLAR JUNCTION TRANSISTOR

A bipolar junction transistor is a three terminal semiconductor device in which the operation depends on the interaction of majority and minority carriers.

## Transistor refers to Transfer Resistor

i.e., signals are transferred from low resistance circuit into high resistance circuit.

BJT BIPOLAR JUNCTION TRANSISTOR consists of silicon crystal in which a layer of ‘N’ type silicon is sandwiched between two layers of ‘P’ type silicon.

The semiconductor sandwiched is extremely smaller in size.

In other words, it consists of two back to back PN junction joined together to form single piece of semiconductor crystal.

These two junctions gives three region called Emitter, Base and Collector.

There are two types of transistors such as PNP and NPN.

The arrow on the emitter specifies whether the transistor is PNP or NPN type and also determines the direction of flow of current, when the emitter base junction is forward biased.

### Emitter:

It is more heavily doped than any of the other region because its main function is to supply majority charge carriers to the base.

### Base:

It forms the middle section of the transistor.

It is very thin as compared to either the emitter or collector and is very lightly doped.

### Collector:

Its main function is to collect the majority charge carriers coming from the emitter and passing through the base.

In most transistors, collector region is made physically larger than the emitter because it has to dissipate much greater power.

## Operation of Transistor

The basic operation will be described using the pnp transistor.

The operation of the pnp transistor is exactly the same if the roles played by the electron and hole are interchanged.

One p-n junction of a transistor is reverse-biased, whereas the other is forward-biased.

Both biasing potentials have been applied to a pnp transistor and resulting majority and minority carrier flows indicated.

Majority carriers (+) will diffuse across the forward-biased p-n junction into the n-type material.

A very small number of carriers (+) will through n-type material to the base terminal. Resulting IB is typically in order of microamperes.

The large number of majority carriers will diffuse across the reverse-biased junction into the p-type material connected to the collector terminal.

Majority carriers can cross the reverse-biased junction because the injected majority carriers will appear as minority carriers in the n-type material.

### Applying KCL to the transistor :

IE = IC + IB

The comprises of two components – the majority and minority carriers

IC = ICmajority + ICOminority

ICO – IC current with emitter terminal open and is called leakage current.

#### Common Base configuration

Common-base terminology is derived from the fact that the :

base is common to both input and output of the configuration.

base is usually the terminal closest to or at ground potential.

All current directions will refer to conventional (hole) flow and the arrows in all electronic symbols have a direction defined by this convention.

Note that the applied biasing (voltage sources) are such as to establish current in the direction indicated for each branch.

To describe the behavior of common-base amplifiers requires two set of characteristics: o Input or driving point characteristics.

Output or collector characteristics

The output characteristics has 3 basic regions:

Active region –defined by the biasing arrangements

Cutoff region – region where the collector current is 0A

Saturation region- region of the characteristics to the left of

VCB = 0V

The curves (output characteristics) clearly indicate that a first approximation to the relationship between IE and IC in the active region is given by

IC ≈IE

Once a transistor is in the ‘on’ state, the base-emitter voltage will be assumed to be

VBE = 0.7V

In the dc mode the level of IC and IE due to the majority carriers are related by a quantity called alpha

α = IC / IE

IC = α IE + ICBO

It can then be summarize to IC = αIE (ignore ICBO due to small value)

For ac situations where the point of operation moves on the characteristics curve, an ac alpha defined by

Alpha a common base current gain factor that shows the efficiency by calculating the current percent from current flow from emitter to collector. The value of  is typical from 0.9 ~ 0.998.

##### Common Emitter configuration

It is called common-emitter configuration since :

emitter is common or reference to both input and output terminals.

emitter is usually the terminal closest to or at ground potential.

Almost amplifier design is using connection of CE due to the high gain for current and voltage.

Two set of characteristics are necessary to describe the behavior for CE; input (base terminal) and output (collector terminal) parameters.

Input characteristics for CE configuration

IB in microamperes compared to milliamperes of IC.

IB will flow when VBE > 0.7V for silicon and 0.3V for germanium

Before this value IB is very small and no IB.

Base-emitter junction is forward bias

Increasing VCE will reduce IB for different values.

Output characteristics for CE configuration

For small VCE (VCE < VCESAT, IC increase linearly with increasing of VCE

VCE > VCESAT IC not totally depends on VCE   — > constant IC

IB(uA) is very small compare to IC (mA). Small increase in IB cause big increase in IC

IB=0 A  — >  ICEO occur.

Noticing the value when IC=0A. There is still some value of current flows.

### Common Collector configuration

• Also called emitter-follower (EF).
• It is called common-emitter configuration since both the
• Signal source and the load share the collector terminal as a common connection point.
• The output voltage is obtained at emitter terminal.
• The input characteristic of common-collector configuration is similar with common-emitter. configuration.
• Common-collector circuit configuration is provided with the load resistor connected from emitter to ground.
• It is used primarily for impedance-matching purpose since it has high input impedance and low output impedance.
• For the common-collector configuration, the output characteristics are a plot of IE vs VCEfor a range of values of IB.

### Small Signal Amplifier

When the input signal is so weak as to produce small fluctuations in the collector current compared to its quiescent value, the amplifier is known as Small Signal Amplifier.

In other words, as the name indicates, the input applied to the circuit is Vin << Vth. It has only one amplifying device.

Α = IC / IE

IC = α  IE + ICBO

Voltage and current equation for hybrid parameters:

V1 = h11i1 + h12V2

I2 = h21i1 + h22V2

The values of h-parameters:

h11 = V1/ i1

h12 = V1 / V2

h21 = i2 / i1

h22 = i2 / V2

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# RECTIFIERS

The rectifiers is a circuit that converts AC voltages and currents into pulsating DC voltages and currents.

It consists of DC components and the unwanted ac ripple or harmonic components which can be removed by using filter circuit.

Thus the output obtained will be steady DC voltage and magnitude of DC voltage can be varied by varying the magnitude of AC voltage.

Filters: A circuit that removes ripples (unwanted ac components) present in the pulsating dc voltage.

Regulator: A circuit that maintains the terminal voltage as constant even if the input voltage or load current varying.

## Types of rectifiers:

Rectifiers are grouped into two categories depending on the period of conduction.

(a)Half wave rectifier

(b) Full wave rectifier

### Half wave Rectifier:

#### Principle

It is a circuit that converts alternating voltage or current into pulsating voltage or current for half the period of input cycle hence it is named as “half wave rectifier”.

##### Construction
• It consists of step-down transformer, semiconductor diode and the load resistance.
•  The step-down transformer – reduce the available ac voltage into required level of smaller ac voltage.
•  The diode can be used to convert the ac into pulsating dc.
###### Operation
• During the positive half cycle of input, the diode D is forward biased, it offers very small resistance and it acts as closed switch and hence conducts the current through the load resistor.
• During the negative half cycle of the input diode D is heavily reverse biased, it offers very high resistance and it acts as open switch hence it does not conduct any current.
• The rectified output voltage will be in phase with AC input voltage for completely resistive load.

### Full wave Rectifier:

#### Principle

A circuit that converts the ac voltage or current into pulsating voltage or current during both half cycle of input is known as “full wave rectifier”.

##### Operation
• During positive half cycle of ac input, diode D1 becomes forward biased, provides very small resistance and acts as closed switch, resulting in the flow of current.
• During negative half cycle, diode D1 reverse biased, offers high resistance and it acts as open circuit.
###### Voltage Regulation:

Ratio of Difference of secondary voltage to Primary voltage to secondary voltage.

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# ZENER EFFECT

ZENER EFFECT: In a general purpose PN diode the doping is light; as a result of this the breakdown voltage is high.

If a P and N region are heavily doped then the breakdown voltage can be reduced.

When the doping is heavy, even the reverse voltage is low, the electric field at barrier will be so strong thus the electrons in the covalent bonds can break away from the bonds.

This effect is known as Zener effect.

## ZENER DIODE

A diode which exhibits the zener effect is called a Zener Diode. Hence it is defined as a reverse biased heavily doped PN junction diode which operates in breakdown region.

The zener diodes have been designed to operate at voltages ranging from a few volts to several hundred volts.

Zener Breakdown occurs in junctions which is heavily doped and have narrow depletion layers.

The breakdown voltage sets up a very strong electric field.

This field is so strong enough to break or rupture the covalent bonds thereby generating electron hole pairs.

Even a small reverse voltage is capable of producing large number of current carrier.

When a zener diode is operated in the breakdown region care must be taken to see that the power dissipation across the junction is within the power rating of the diode otherwise heavy current flowing through the diode may destroy it.

## V-I characteristics of Zener diode

The illustration above shows this phenomenon in a current vs voltage graph with a zener diode connected in the forward direction.

It behaves exactly as a standard diode.

In  the  reverse  direction  however  there  is  a  very  small  leakage  current  between  0v and the zener voltage

i.e. just a tiny amount of current is able to flow.

Then, when the voltage reaches the breakdown voltage (vz),suddenly current can flow freely through it.

### Application of Zener diode

• As voltage regulator
• As peak clippers
• For reshaping waveforms

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# PN JUNCTION DIODE

PN JUNCTION DIODE:

A p–n junction is formed by joining P-type and N-type semiconductors together in very close contact.

The term junction refers to the boundary interface where the two regions of the semiconductor meet.

Diode is a two-terminal electronic component that conducts electric current in only one direction.

The crystal conducts conventional current in a direction from the p-type side (called the anode) to the n-type side (called the cathode), but not in the opposite direction.

## Symbol of PN junction diode

### Biasing

Biasing” is providing minimum external voltage and current to activate the device to study its characteristics.

There are two operating regions and two “biasing” conditions for the standard Junction Diode and they are

### Zero Bias:

When a diode is Zero Biased no external energy source is applied and a natural Potential Barrier is developed across a depletion layer.

#### (i) Forward Bias:

When the positive terminal of a battery is connected to P-type semiconductor and negative terminal to N-type is known as forward bias of PN junction.

The applied forward potential establishes an electric field opposite to the potential barrier.

Therefore the potential barrier is reduced at the junction. As the potential barrier is very small (0.3V for Ge and 0.7V for Si),a small forward voltage is sufficient to completely eliminate the barrier potential, thus the junction resistance becomes zero.

In otherwords, the applied positive potential repels the holes in the ‘P’ region so that the holes moves towards the junction and applied negative potential repels the electrons in the ‘N’ region towards the junction results in depletion region starts decreasing.

When the applied potential is more than the internal barrier potential then the depletion region completely disappear, thus the junction resistance becomes zero.

Once the potential barrier is eliminated by a forward voltage, j unction establishes the low resistance path for the entire circuit, thus a current flows in the circuit, it is called as forwardcurrent.

#### (ii)Reverse Bias:

For reverse bias, the negative terminal is connected to P-type semiconductor and positive terminal to N type semiconductor.

When reverse bias voltage is applied to the junction, all the majority carriers of ‘P’ region are attracted towards the negative terminal of the battery and the majority carriers of the N region attracted towards the positive terminal of the battery, hence the depletion region increases.

The applied reverse voltage establishes an electric field which acts in the same direction of the potential barrier.

Therefore, the resultant field at the junction is strengthened and the barrier width is increased.

This increased potential barrier prevents the flow of charge carriers across the junction, results in a high resistance path.

This process cannot continue indefinitely because after certain extent the junction break down occurs.

As a result a small amount of current flows through it due to minority carriers. This current is known as “reverse saturation current”.

## V I characteristics of PN junction diode

### Forward Bias:

The application of a forward biasing voltage on the junction diode results in the depletion layer becoming very thin and narrow which represents a low impedance path through the junction thereby allowing high currents to flow.

The point at which this sudden increase in current takes place is represented on the static I-V characteristics curve above as the “knee” point.

### Reverse Bias:

In Reverse biasing voltage a high resistance value to the PN junction and practically zero current flows through the junction diode with an increase in bias voltage.

However, a very small leakage current does flow through the junction which can be measured in microamperes, (μA).

One final point, if the reverse bias voltage Vr applied to the diode is increased to a sufficiently  high enough value, it will cause the PN junction to overheat and fail due to the avalanche effect around the junction.

This may cause the diode to become shorted and will result in the flow of maximum circuit current, and this shown as a step downward slope in the reverse static characteristics curve below.

To see other topics in Basic Electrical and Electronics Engineering Click here

Construction of DC GENERATOR

Semiconductor Devices And Applications

Classification of Materials

Classification of Semiconductor

Zener Effects

Rectifiers and Types of rectifiers

Bipolar Junction Transistor(BJT)