EC6302 Digital Electronics Question Bank
EC6302 Digital Electronics Question Bank Regulation 2013 Anna University free download. Digital Electronics EC6302 Question Bank pdf free download.
Sample EC6302 Digital Electronics Question Bank:
Part – A 2 mark
1. Apply De-Morgan’s theorem to simplify A+BC.
2. Define the term prime implicants and Essential prime implicants.
3. Draw the XOR logic using only NAND gates.
4. Implement the following Boolean function with NOR – NOR logic
F = Π(0,2, 4,5,6)
5. Express the switching function f (ABC) = B in terms of minterm. (EC6302 Digital Electronics Question Bank)
6. Define minterm & Maxterm. Give examples.
7. Simplify the given Boolean Expression F= x’+xy+xz’+xy’z’.
8. Prove that the logical sum of all minterms of a Boolean function of 2 variables is 1.
9. Show that a positive logic NAND gate is a negative logic NOR gate.
10. If A & B are Boolean variables and if A=1 & A+B=0, Find B? (EC6302 Digital Electronics Question Bank)
11. Realize F = A’B+AB’ using minimum universal gates.
12. Write the Boolean expression for the output of the system shown in figure.
13. Write down fan-in & fan-out of a standard TTL IC.
14. Prove that AB+A’C+BC = AB + A’C
15. Implement the following Boolean function with NAND – NAND logic
F = Σ(0,1, 3, 5) (EC6302 Digital Electronics Question Bank)
16. What are don’t care terms?
17. What are universal gates implement AND gate using any one universal gate?
18. What are the advantages of Schottky TTL family?
19. Define the term (i). Propagation delay (ii). Power dissipation
20. Draw an active high tri-state Gate & write its truth table. (EC6302 Digital Electronics Question Bank)
Part – B 16 mark
1. a). i). Simplify the following function using K – map, f=ABCD+AB’C’D’+AB’C+AB &
realize the SOP using only NAND gates and POS using only NOR gates (12)
ii). Simplify the logic circuit shown in figure (4)
2. a). i). Minimize the term using Quine McCluskey method & verify the result using Kmap
method πM(0,1,4,11,13,15)+ πd(5,7,8). (10)
ii). Explain the operation of 3 input TTL NAND gate with required diagram & truth
table. (6)
3. a). i). Using K-map method, Simplify the following Boolean function and obtain
(a) minimal SOP and
(b) minimal POS expression & realize using only NAND and NOR gates
F=Σm(0,2,3,6,7) + d(8,10,11,15) (10)
ii). Draw the circuits of 2 input NAND & 2 input NOR gate using CMOS (6) (EC6302 Digital Electronics Question Bank)
| Subject Name | Digital Electronics |
| Subject Code | EC6302 |
| Regulation | 2013 |
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