**EC8095 Important Questions VLSI Design**

EC8095 Important Questions VLSI Design Regulation 2017 Anna University free download. VLSI Design Important Questions EC8095 pdf free download.

**Sample EC8095 Important Questions VLSI Design**

1.

Explain the structure and working of nMOS and pMOS

transistor. (13)

BTL 4 Analyzing

2.

Summarize the following using CMOS logic:

(i) Inverter with truth table, (6)

(ii) NAND Gate with truth table. (7)

BTL 2 Understanding

3.

Illustrate with necessary diagrams

(i) Ideal I-V characteristics of MOS transistors, (6)

(ii) C-V characteristics of MOS transistors. (7)

BTL 3 Applying

4.

Analyze the characteristics and working of the following with

neat diagram,

(i) Pass transistors, (6)

(ii) Transmission gate. (7)

EC8095 Important Questions VLSI Design

(i) Describe in detail about Layout design rules. (7)

(ii) Draw the stick diagram and layout diagram for the CMOS

gate computing. Y (A B C) D . (6)

BTL 1 Remembering

6.

Discuss in detail about the velocity saturation and channel

length modulation. (13)

BTL 2 Understanding

7.

Write short notes on:

(i) Body Effect, (4)

(ii) Subthreshold Condition, (4)

(iii) Junction Leakage. (5)

EC8095 Important Questions VLSI Design

Interpret the DC transfer characteristics of CMOS inverter.

(13)

BTL 3 Applying

9.

Describe the following with necessary equations.

(i) Detailed MOS gate capacitance model, (7)

(ii) Detailed MOS diffusion capacitance model. (6)

BTL 2 Understanding

10.

Demonstrate the RC Delay model and Elmore delay model.

EC8095 Important Questions VLSI Design

(i) State logical effort and draw the logic gates for different

transistor widths. (6)

(ii) Define parasitic delay and compare the parasitic delay of

common gates for various inputs. (7)

BTL 1 Remembering

12.

Write short notes on:

(i) Transistor scaling, (7)

(ii) Interconnect scaling. (6)

BTL 1 Remembering

13.

Design a CMOS inverter and formulate the beta ratio effects

and noise margin. (13)

EC8095 Important Questions VLSI Design

Evaluate Multistage Logic Networks with delay and formulate

the expression with an example.

Subject name | VLSI Design |

Short Name | VLSI |

Semester | 6 |

Subject Code | EC8095 |

Regulation | 2017 regulation |

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