CS6801 Important Questions Multi Core Architectures and Programming

CS6801 Important Questions Multi Core Architectures and Programming Regulation 2013 Anna University free download. Multi Core Architectures and Programming CS6801 Important Questions pdf free download.

Sample CS6801 Important Questions Multi Core Architectures and Programming:

1. Difference between symmetric memory and distributed architecture.
Symmetric memory: It consists of several processors with a single physical memory shared by all processors through a shared bus.
Distributed memory:It is a form of memory architectures where the memories can be addressed as one address space.
2. What is vector instruction? CS6801 Important Questions Multi Core Architectures and Programming
These are instructions that operate on vectors rather than scalars. if the vector length is vector length, these instructions have the great virtue that a simple loop such as
For(i=0;i<n;i++)
X[i]+=y[i];
Requires only a single load, add and store for each block of vector length elements, while a conventional system requires a load, add and store for each element.
3. What are the factors to increasing the operating frequency of the processor?
(i)Memory wall
(ii)ILP wall
(iii)Power wall

10. What is called directory based? CS6801 Important Questions Multi Core Architectures and Programming
Sharing status of a block of physical memory is kept in just one location called the directory.
11. What are the issues available in handling the performance?
(i)Speedup and efficiency
(ii) Amdahl’s law
(iii)Scalability
(iv)Taking timings
12. What are the disadvantages of symmetric shared memory architecture?
(i)Complier mechanisms for transparent software cache coherence are very limited. CS6801 Important Questions Multi Core Architectures and Programming
(ii)Without cache coherence, the multiprocessor loses the advantage of being to fetch and use multiple words, such as a cache block and where the fetch data remain coherent.
13. Write a mathematical formula for speedup of parallel program.
Speedup=TserialTparallel
14. Define – False sharing
It is the situation where multiple threads are accessing items of data held on a single cache line. CS6801 Important Questions Multi Core Architectures and Programming

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